The present invention relates generally to packaging semiconductor devices and more specifically systems and methods for packaging semiconductor devices using materials having significantly mismatched coefficients of thermal expansion (CTEs).
The power dissipated by electronic semiconductor packages such as ASICs/microprocessors continues to grow with the demand for higher performance. This growth in power dissipation requirements has grown at an unabated rate in recent years. Thermal engineers often consider the use of newer, high conductivity materials in the semiconductor package stack to enable effective transfer of the heat generated in the semiconductor devices.
FIG. 1 is a simplified diagram of a typical semiconductor package stack 100. The package stack 100 includes a cavity-based lid 102, a semiconductor device die 104, a die-lid thermal interface material (TIM1) 110, and a substrate 120. A heatsink 130 and a lid-heatsink thermal interface material (TIM2) 132 are also shown.
The ability to transfer heat away from the die 104 assumes that the package stack 100 can be assembled in the first place. The different materials used in the high conductivity lid 102, TIM1 110 and substrate 120 can often be incompatible with each other from a thermal expansion perspective (as quantified using the Coefficient of Thermal Expansion, or CTE). As a result, assembly of the package stack 100 can be a significantly difficult task with part failures occurring during lid attach, cure and standard temperature cycle testing.
FIG. 2 is a simplified diagram of an incompatible package stack 200. As the temperatures in the stack 200 increase or decrease, the different CTE can cause the lid 102 to deform. Spaces 202 and 204 can be formed as the lid 102 deforms. Spaces 202 between the edge of the lid 102 and the substrate 120 are referred to as edge delamination. Space 204 between the die 104 and the central portion of the lid 102 is referred to die-level delamination. Typically the edge delamination and the die-level delamination occur after TIM1 110 is cured and/or during temperature cycling. The spaces 202 and 204 prevent the heat from being effectively transferred from the die 104 to the lid 102 and from the lid to the substrate 120.
While being an excellent idea in principle, the actual use of high conductivity materials in the lid 102 and the TIM1 110 in the package stack becomes substantially difficult, if not impossible to implement in practical applications when the materials have significant CTE mismatches. In view of the foregoing, there is a need for a system and method of overcoming the physical issues associated with the mismatched CTEs.